The present invention relates to a testing technique for a plurality of memories which are different in access data width and address decode logic and more specifically to the technique which can be effectively applied, for example, to a microcomputer which is provided with a plurality of on-chip memories or to a semiconductor integrated circuit such as so-called system LSI.
The Japanese Unexamined Patent Publication Nos. 2000-111618 and Hei11 (1999)-250698 are typical references describing the testing technique for a plurality of on-chip memories of a semiconductor integrated circuit of microcomputer and system LSI. These references also describe bit expansion of test data in the preceding stage of the on-chip memory.
Moreover, in the memory test, it is required to consider the influence of interference between memory cells, word line disturbance and bit line disturbance to ensure random access and therefore it is not practical to verify all cases because a large amount of testing time. Accordingly, as a method for effective verification, a method such as march pattern or walking pattern has been employed. In the verification method of this type, it is necessary to change the selecting direction of memory cells for physical allocation thereof depending on the predetermined rule wherein data is updated to the predetermined value while the memory cells of access unit are sequentially selected in the row direction for the memory cell array or while the memory cells are sequentially selected in the column direction.